Use of a silicon-on-insulator, or SOI, substrate generally enables the manufacture of typical circuit elements over an insulator, such as oxide. In one application, capacitorless DRAMs may be formed on SOI. Use of the SOI design versus a traditional silicon substrate increases the floating body effect for the access transistors of these capacitorless DRAMs, yielding far more effective storage. The programming of the floating bodies in such DRAMs may be done either by impact ionization (“II”) or by gate induced drain leakage (“GIDL”). The sensing is non-destructive and is done using a resistance or current sensing method at a lower voltage. Further description of capacitorless DRAM via GIDL may be found in Yoshida et al., A Design of a Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory, Technical Digest—International Electron Devices Meeting 2003, pp. 913-916 (IEEE Cat. No. 03CH37457, 2003), the contents of which are incorporated herein in its entirety.